1. Field of the Invention
The present invention relates to phase lock loop circuits, and in particular, circuitry within the feedback loop for controlling the oscillator and minimizing phase noise and spurious signal content.
2. Description of the Related Art
Referring to FIG. 1, a typical conventional phase lock loop circuit 10 includes an oscillator 12 (typically a voltage-controlled oscillator, or VCO) which is driven by a control signal 25 to produce its oscillator output signal 13. This output signal 13 is fed back to a prescaler 14 which divides down the frequency of this signal 13. The reduced frequency signal 15 is then further divided down by a counter 16 having a programmable divisor N. The final frequency-divided signal 17 is provided to a phase detector 20.
A reference signal 11 provided by an external reference oscillator (not shown) is divided down in frequency by another counter 18 having another programmable divisor R. The resultant frequency-divided signal 19 is also provided to the phase detector 20. The phase detector 20 compares the relative phases of these two signals 17, 19, using the frequency-divided reference signal 19 as the xe2x80x9ctargetxe2x80x9d with respect to the desired phase of the feedback signal 17. (This phase comparison is done in accordance with well-known conventional techniques and hence need not be described further here.) Based upon this phase comparison, the phase detector provides two phase signals 21u, 21d. One of the signals 21u is asserted when it is necessary to increase the frequency of the feedback signal 17 in order to have its phase match that of the reference signal 19. The other signal 21d is asserted when it is necessary for the frequency of the feedback signal 17 to be decreased in frequency so as to have its signal phase match that of the reference signal 19.
These two phase signals 21u, 21d are provided to a charge pump circuit 22 (discussed in more detail below) which provides an output current signal 23i and a feedback signal 23f. The output current signal 23i is used to xe2x80x9cpump upxe2x80x9d or xe2x80x9cpump downxe2x80x9d the electrical charge stored by a capacitor (not shown) within the loop filter circuit 24 in accordance with well known conventional techniques. As a result of this stored electrical charge, the loop filter 24 provides the control signal 25 for the oscillator 12. The feedback signal 23f is used to control the assertion and deassertion of the phase signals 21u, 21d generated by the phase detector 20.
Referring to FIG. 2, a conventional embodiment 22a of the charge pump 22 (FIG. 1), includes an input buffer 102u/102d, such as an inverter, a bias circuit 104u/104d and a current source circuit 106u/106d for each of the xe2x80x9cpump upxe2x80x9d and xe2x80x9cpump downxe2x80x9d signal channels. For each channel, the incoming signal 21 is buffered and inverted by the inverter 102u/102d. The resulting inverted input signal 103u/103d drives the bias circuit 104u/104d and the current source circuit 106u/106d. Assertion of this signal 103u/103d causes the bias circuit 104u/104d to generate a bias signal 105u/105d. Coincident assertions of this inverted input signal 103u/103d and bias signal 105u/105d cause the current source circuit 106u/106d to generate its output current 107u/107d. For the xe2x80x9cpump upxe2x80x9d channel, the output signal 107u is a source current, while for the xe2x80x9cpump downxe2x80x9d channel, the output current 107d is a sink current. These source 107u and sink 107d currents sum at the output note 108 to produce the net, or composite, output current 23i. 
Referring to FIG. 3 (in conjunction with FIG. 2), it can be seen that during a charge pump event (either pump up or pump down) the bias 104u/104d and current source (or sink) 106u/106d circuitry are both enabled by their corresponding phase signal 21 and bias signal 105u/105d. However, the bias circuitry 104u/104d takes a longer interval of time to become fully enabled, or turned on, than the current source (or sink) circuitry 106u/106d. And, since the bias circuitry 104u/104d must be turned on before the current source (or sink) circuitry 106u/106d can effectively generate its output current 107u/107d and thereby provide the appropriate charge to the loop filter 24 (FIG. 1), the leading and trailing edges of the output current 23i waveform are dictated by how fast the bias circuitry 104u/104d turns on. Hence, the net output current 23i has slow rise and fall times which cause the output current signal 23i to have significant low frequency signal components. These low frequency signal components cannot be effectively filtered out by the lowpass loop filter 24. As a result, these low frequency signal components appear as phase noise or spurious signals within the output signal 13 from the oscillator 12 (FIG. 1).
As noted above, the feedback signal 23f determines when the phase signals 21u, 21d from the phase detector 20 are deasserted. Upon coincident assertion of the output source 107u and sink 107d currents, the feedback signal 23f is asserted, following which the phase signals 21u, 21d from the phase detector 20 are deasserted. Such coincident assertions of the source 107u and sink 107d currents are detected by a monitor circuit 110 which monitors these currents (in a conventional manner) to produce the feedback signal 23f. 
Accordingly, it would be desirable to have an oscillator control circuit capable of generating charge pump current signals with significantly reduced low-frequency signal components so as to minimize in-band phase noise and spurious signals associated with such low-frequency signal components.
An oscillator control circuit for a phase lock loop in accordance with one embodiment of the present invention provides source and sink currents at the output of the charge pump circuitry with high slew rates. The fast rise and fall times of the waveforms for these current signals cause minimal low-frequency signal components to be included in the frequency spectrum of the output signals. Instead, any harmonics or other signal components associated with these waveforms occur at significantly higher frequencies, thereby allowing them to be filtered out by the loop filter before reaching the oscillator. Additionally, these fast rise and fall times for the current signal pulses cause such signal pulses to be of shorter durations, thereby minimizing the amount of spurious signal energy being produced. Furthermore, these fast signal pulse edges translate into a higher effective charge pump output signal relative to the noise, thereby resulting in an increased signal-to-noise ratio (SNR) and hence an improvement in phase noise. Hence, in-band phase noise and spurious signal content are significantly reduced.
An apparatus including oscillator control circuitry for a phase lock loop in accordance with one embodiment of the present invention includes phase detection circuitry, control signal generator circuitry, bias control circuitry and charge pump circuitry. The phase detection circuitry, responsive to a reference signal, an oscillator feedback signal and a charge pump feedback signal, provides first and second phase signals indicative of a phase difference between the reference and oscillator feedback signals with respective assertion states responsive to the phase difference and respective deassertion states responsive to the charge pump feedback signal. The control signal generator circuitry, coupled to the phase detection circuitry and responsive to the first and second phase signals, provides: a first pump control signal with assertion and deassertion states corresponding to and time-delayed from the first phase signal assertion and deassertion states; a first bias control signal with assertion and deassertion states responsive to the first phase signal and the first pump control signal; a second pump control signal with assertion and deassertion states corresponding to and time-delayed from the second phase signal assertion and deassertion states; and a second bias control signal with assertion and deassertion states responsive to the second phase signal and the second pump control signal. The bias control circuitry, coupled to the control signal generator circuitry and responsive to the first and second bias control signals, provides first and second bias enablement signals with assertion and deassertion states. The charge pump circuitry, coupled to the bias control circuitry and the control signal generator circuitry and responsive to the first and second bias enablement signals and the first and second pump control signals, provides a composite output current signal and the charge pump feedback signal, wherein: the composite output current signal includes an output source current component substantially coincident with the first bias enablement and pump control signal assertion states and includes an output sink current component substantially coincident with the second bias enablement and pump control signal assertion states; and the charge pump feedback signal includes an assertion state responsive to a coincidence of the output source and sink current components.